1. Field of the Invention
The present invention relates generally to a reset circuit and, more particularly, to a reset circuit used for resetting when switching on a power supply of an integrated circuit integrated on a semiconductor substrate. The present invention also relates to an integrated circuit including this reset circuit.
2. Description of the Prior Art
A conventional resetting practice when turning on a power supply of an integrated circuit formed on a semiconductor substrate is to provide a reset circuit for generating a reset signal at the power-on, externally or internally of the integrated circuit and to conduct resetting operation necessary at power-on.
FIGS. 5 and 6 are block diagrams each showing one example of the conventional reset circuit. In the circuit illustrated in FIG. 5, a reset circuit 20 is constructed by series-connecting a capacitor C and a resistor R to which a diode is connected in parallel. An output terminal of the reset circuit 20 is connected to a reset terminal of an integrated circuit 10 and a reset signal generated at the power-on is applied thereto.
Further, in a circuit shown in FIG. 6, a reset circuit 20a is constructed of a constant voltage power circuit. An output signal VOUT thereof is supplied to the reset terminal of the integrated circuit 10.
The conventional reset circuits, however, have a limit in terms of capability to generate the reset signal at the power-on time, depending on a magnitude of a power voltage employed by the integrated circuit receiving the reset signal and conditions such as a slope of rise of the power voltage at the power-on and so forth. For example, in the C-R reset circuit illustrated in FIG. 5, the slope of rise of the power voltage at the power-on is restricted due to the circuit characteristics. Therefore, there has been a problem in that the circuit can not be used in the case of the slope being smaller than a certain level.
Furthermore, a reset circuit for generating the reset signal by use of the constant voltage power circuit shown in FIG. 6 presents a problem that there exists a limit in terms of a magnitude of the power voltage used by the integrated circuit receiving the reset signal because of the circuit characteristics. Accordingly, the circuit can not be used in the case of a power voltage being smaller than a certain level.